FMA4 on Matisse?

[Melzzzzz]

FMA4 works on my 2700X. Question is: is that supported
still on Zen2?
Instructions are not reported at all by cpuid but works.
I had some nice speedup with FMA4 on Zen.
I don't know why FMA3 won when FMA4 is clearly superior?

[Bonita Montero]

Post by Melzzzzz
FMA4 works on my 2700X. Question is: is that supported
still on Zen2?
Instructions are not reported at all by cpuid but works.
I had some nice speedup with FMA4 on Zen.
I don't know why FMA3 won when FMA4 is clearly superior?

When dealing with floating-point-operations you have a lot of
instructions with long latencies. Even if you have parallel chains
of instructions that could be pipelined, there are mostly oppurtu-
nities to hide movs that might be necessary to prevent overwriting
registers. And often their value isn't needed to be remembered. So
your speedup could be only slightly and sometimes there's nothing
at all.

[Anton Ertl]

Post by Melzzzzz
FMA4 works on my 2700X. Question is: is that supported
still on Zen2?
Instructions are not reported at all by cpuid but works.
I had some nice speedup with FMA4 on Zen.
I don't know why FMA3 won when FMA4 is clearly superior?

Intel supports FMA3, but not FMA4.

If your question is why they do that, I can only speculate:

1) Well-placed register-register moves can have latency 0 and cost no
execution unit resources, only some front-end resources, because the
register renamer eliminates them. So the advantage of FMA4 on Intel
may be miniscule (not sure if the Zen register renamer works the same
way; if so, maybe you can get similar performance with FMA3 if you
arrange the move appropriately).

2) FMA4 may require complications in the instruction decoder and
register renamer that the Intel engineers were not prepared to pay
for, given the small benefit.

- anton

[Bonita Montero]

Post by Anton Ertl
1) Well-placed register-register moves can have latency 0 and cost no
execution unit resources, only some front-end resources, because the
register renamer eliminates them.

It takes one decoder-slot and thereby will delay other instructions
which go to the next decoded bundle.